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TECHNICAL NOTE
Large Current External FET Controller Type Switching Regulator
Step-down, High-efficiency Switching Regulators (Controller type)
BD9011EKN , BD9011KV , BD9775FV
BD9011EKN, BD9011KV Overview The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It supports a wide input range, enabling low power consumption ecodesign for an array of electronics. Features 1) Wide input voltage range: 3.9V to 30V 2) Precision voltage references: 0.8V1% 3) FET direct drive 4) Rectification switching for increased efficiency 5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz) 6) Built-in selected OFF latch and auto remove over current protection 7) Built-in independent power up/power down sequencing control 8) Make various application , step-down , step-up and step-up-down 9) Small footprint packages: HQFN36V, VQFP48C Applications Car audio and navigation systems, CRTTVLCDTVPDPTVSTBDVDand PC systemsportable CD and DVD players, etc. Absolute Maximum Ratings (Ta=25) Parameter
EXTVCC Voltage VCCCL1,2 Voltage CL1,2 Voltage SW1,2 Voltage BOOT1,2 Voltage BOOT1,2-SW1,2 Voltage STB, EN1,2 Voltage VREG5,5A VREG33 SS1,2FB1,2
Symbol
EXTVCC VCCCL1,2 CL1,2 SW1,2 BOOT1,2 BOOT1,2-SW1,2 STB, EN1,2 VREG5,5A VREG33 SS1,2FB1,2
Rating
34 34
*1 *1
Unit
V V V V V V V V V V
Parameter
COMP1,2 Voltage DET1,2 Voltage RTSYNC Voltage
Symbol
COMP1,2 DET1,2 RTSYNC
Rating
VREG5
Unit
V
34 34 40 7
*1 *1
0.875 HQFN36V Power Dissipation Pd 1.1 VQFP48C
*2
*2
W
*1
W
VCC 7 VREG5 VREG5
Operating temperature Storage temperature Junction temperature
Topr Tstg Tj
-40 to +105 -55 to +150 +150

*1 Regardless of the listed rating, do not exceed Pd in any circumstances. *2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/HQFN36V or 8.8mW/VQFP48C above 25.
Sep. 2008
Operating conditions (Ta=25) Parameter Input voltage 1 Input voltage 2 BOOTSW voltage Carrier frequency Synchronous frequency Synchronous pulse duty Min OFF pulse
*1 After more than 4.5V, voltage range. *2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.
Symbol EXTVCC VCC BOOTSW OSC SYNC Duty TMIN
Min. 3.9
*1 *2
Typ. 12 12 5 300 50 100
Max. 30 30 VREG5 550 550 60 -
Unit V V V kHz kHz nsec
3.9 *1 *2 4.5 250 OSC 40 -
This product is not designed to provide resistance against radiation.
Electrical characteristics (Unless otherwise specified, Ta=25 VCC=12V STB=5V EN1,2=5V) Parameter VIN bias current Shutdown mode current Error Amp Block Feedback reference voltage Feedback reference voltage (Ta=-40 to 105) Open circuit voltage gain VO input bias current FET Driver Block HG high side ON resistance HG low side ON resistance LG high side ON resistance LG low side ON resistance Oscillator Carrier frequency Synchronous frequency Over Current Protection Block CL threshold voltage CL threshold voltage Ta=-40 to 105 VREG Block VREG5 output voltage VREG33 reference voltage VREG5 threshold voltage VREG5 hysteresis voltage Soft start block Charge current ISS 6.5 10 13.5 14 A A VSS=1V VSS=1V,Ta=-40 to 105 Charge current ISS+ 6 10 (Ta=-40 to 105) Note: Not all shipped products are subject to outgoing inspection. 2/29 VREG5 VREG33 VREG_UVLO DVREG_UVLO 4.8 3.0 2.6 50 5 3.3 2.8 100 5.2 3.6 3.0 200 V V V mV IREF=6mA IREG=6mA VREG:Sweep down VREG:Sweep up Vswth Vswth+ 70 67 90 90 110 113 V V Ta=-40 to 105 FOSC Fsync 270 300 500 330 kHz kHz RT=100 k RT=100 k,SYNC=500kHz HGhon HGlon LGhon LGlon 1.5 1.0 1.5 0.5 VOB VOB+ Averr IVo+ 0.792 0.784 0.800 0.800 46 0.808 0.816 1 V V dB A Ta=-40 to 105 Symbol IIN IST Limit Min. Typ. 5 0 Max. 10 10 Unit mA A VSTB=0V Conditions
Reference data (Unless otherwise specified, Ta=25)
100 90 80 EFFICIENCY[%] 70 60 50 40 30 20 10 0 0 2.6V 3.3V
5.0V
100 90 3.3V CIRCUITCURRENT[mA] 80 EFFICIENCY[%]
6 5
1.8V 1.2V
70 60 50 40 30 20
5.0V
4 3 2 1 0
105
25
-40
VIN=12V
1 2 OUTPUT CURRENTIo[A] 3
10 0 6 9
Io=2A
12 15 18 21 INPUT VOLTAGE VIN[V] 24
0
10 20 INPUT VOLTAGEVIN[V]
30
Fig.1 Efficiency 1
Fig.2 Efficiency 2
Fig.3 Circuit current
0.816 REFERENCE VOLTAGE VOB[V] Vswth[mV] 0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE Ta[]
110
OSILATING FREQUENCY F OSC[kHz]
330 320 310 300 290 280 270
RT=100k
100
90 80
70 60 -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE Ta[]
-40
-15
10
35
60
85
110
AMBIENT TEMPERATURE Ta[]
Fig.4 Reference voltage vs. temperature characteristics
5.25 5.00 OUT PUT VOLTAGE Vo[V]
Fig.5 Over current detection vs. temperature characteristics
6 5
OUT PUT VOLTAGE Vo[V] 3.0 2.5
Fig.6 Frequency vs. temperature characteristics
4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 -40 -15 10
OUT PUT VOLTAGE Vo[V]
VREG5
5.0V
4 3
RCL=15m
2.0 1.5
3.3V
2 1 0 0 5 10 15 20 INPUT VOLTAGE VIN[V] 25
LOFF=H
1.0
VREG33
LOFF=L
0.5 0.0 0 1 2 3 4 5 6 OUTPUT CURRENT: Io[A]
35
60
85
110
AMBIENT TEMPERATURE Ta[]
Fig.7 Internal Reg vs. temperature characteristics
6
Fig.8 Line regulation
Fig.9 Load regulation
OUTPU TVOLTAGE Vo[V]
5
50mV/div VOUT VOUT
50mV/div
4 105 3 25 2 1 0 0 2 4 INPUT VOLTAGEV EN[V] 6 -40
IOUT 1A/div IOUT 1A/div
Fig.10 EN threshold voltage
Fig.11 Load transient response 1
Fig.12 Load transient response 2
3/29
Block diagram
(Parentheses indicate VQFP48C pin numbers)
EXTVCC
22 (41)
5V Reg
STB VCC
10 (25) 32 (7)
RT
15 (33)
SYNC
16 (34)
3.3V Reg
VREG5
24(44) B.G SYNC
5(19) 17(35)
UVLO TSD 2.7V
VREG33 LLM VCCCL1 CL1 BOOT1 OUTH1 SW1 VREG5A OUTL1 DGND1 FB1 SS1 COMP1
TSD
OSC 33(8) 34(10)
VCCCL2 CL2 BOOT2 OUTH2 SW2 OUTL2 DGND2 FB2 SS2 COMP2
31(5) 30(3) 29(2) 28(1) 27(48)
OCP Set DRV Reset Set Reset DRV
OCP
35(11) 36(12)
SW
VREG5
SW
TSD UVLO Q Reset Set PW M COMP TSD UVLO
1(13) 4(17) 3(15) 2(14)
LOGIC
LOGIC
25(46) 26(47) 21(39) 19(37) 20(38)
0.8V
Slope
Slope
PW M COMP
Q Set Reset
Err Amp
Err Amp
6(21) 8(23)
0.8V
UVLO
7(22)
Q Q Reset Sequence DET Set
Set Reset Sequence DET
0.56V
0.56V
18 (36)
14 (31)
12 (27)
11 (26)
(30)
13 (29)
9 (24)
DET2
LOFF
EN2
EN1 (GNDS) GND
DET1
Fig-13
Pin configuration BD9011EKNHQFN36V
EXTVCC
PIN function table
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name SW1 DGND1 OUTL1 VREG5A VREG33 FB1 COMP1 SS1 DET1 STB EN1 EN2 GND LOFF RT SYNC LLM DET2 SS2 COMP2 FB2 EXTVCC VREG5 OUTL2 DGND2 SW2 OUTH2 BOOT2 CL2 VCCCL2 VCC VCCCL1 CL1 BOOT1 OUTH1 Function High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 FET drive REG input Reference input REG output Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1ON/OFF pin Output 2ON/OFFpin Ground Over current protection OFF latch function ON/OFF pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 External power input pin N.C. FET drive REG output Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 Hi side FET gate drive pin 2 OUTH2 driver power pin Over current detector setting pin 2 Over current detection VCC2 Input power pin Over current detection VCC1 Over current detector setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1
COMP2
20
DGND2
VREG5
OUTL2
SW2
27
26
25
24
23
22
21
OUTH2 28 BOOT2 29 CL2 30 VCCCL2 31 VCC 32 VCCCL1 33 CL1 34 BOOT1 35 OUTH1 36
1 2 3 4 5 6 7 8 9
SS2
19 18 DET2 17 LMM 16 SYNC 15 RT 14 LOFF 13 GND 12 EN2 11 EN1 10 STB
SW1
VREG33
FB1
FB2 COMP1
DGND1
OUTL1
SS1
VREG5A
Fig-14
DET1
4/29
Pin configuration BD9011KVVQFP48C
GNDS SYNC
Pin function table
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name OUTH2 BOOT2 CL2 N.C VCCCL2 N.C VCC VCCCL1 N.C CL1 BOOT1 OUTH1 SW1 DGND1 OUTL1 N.C VREG5A N.C VREG33 N.C FB1 COMP1 SS1 DET1 STB EN1 EN2 N.C GND GNDS LOFF N.C RT SYNC LLM DET2 SS2 COMP2 FB2 N.C EXTVCC N.C N.C VREG5 N.C OUTL2 DGND2 SW2 Function High side FET gate drive pin 2 OUTH2 driver power pin Over current detection pin 2 Non-connect (unused) pin Over current detection VCC2 Non-connect (unused) pin Input power pin Over current detection CC1 Non-connect (unused) pin Over current detection setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 Non-connect (unused) pin FET drive REG input Non-connect (unused) pin Reference input REG output Non-connect (unused) pin Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1 ON/OFF pin Output 2 ON/OFF pin Non-connect (unused) pin Ground Sense ground Over current protection OFF latch function ON/OFF pin Non-connect (unused) pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 Non-connect (unused) pin External power input pin Non-connect (unused) pin Non-connect (unused) pin FET drive REG output Non-connect (unused) pin Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2
LOFF
DET2
GND
36
35
34
33
32
31
30
29
28
27
EN1
26
STB
25 24 DET1 23 SS1 22 COMP1 21 FB1 20 N.C 19 VREG33 18 N.C 17 VREG5A 16 N.C 15 OUTL1 14 DGND1 13 SW1 12
LLM
SS2 37 COMP2 38 FB2 39 N.C 40 EXTVCC 41 N.C 42 N.C 43 VREG5 44 N.C 45 OUTL2 46 DGND2 47 SW2 48
1 2 3 4 5 6 7 8 9 10 11
EN2
N.C
N.C
RT
BOOT2
BOOT1
N.C
N.C
VCC
N.C
OUTH2
VCCCL2
Fig-15
Block functional descriptions
Error amp The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage. Oscillator (OSC) Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz. SLOPE The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator. PWM COMP The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum. Reference voltage (5Vreg33Vreg) This block generates the internal reference voltages: 5V and 3.3V. External synchronization (SYNC) Determines the switching frequency, based on the external pulse applied. Over current protection (OCP) Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low, and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch mode ends when the latch is set to STB, EN. Sequence control (Sequence DET) Compares FB voltage with reference voltage (0.56V) and outputs the result as DET. Protection circuits (UVLO/TSD) The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or exceeds 150. Output is restored when temperature falls back below the threshold value.
VCCCL1
OUTH1
CL2
CL1
5/29
Application circuit example (Parentheses indicate VQFP48C pin numbers)
VIN(12V)
100uF
15m 100 1nF
0.33
15m 10 1nF
32
(7)
SP8K2
RB160 VA-40
uF
100
SP8K2
RB160 VA-40
36
(12)
35
(11)
34
(10)
33
(8)
31
(5)
30
(3)
29
(2)
28
(1)
(SLF12565TDK) Vo(5V/3A) 10uH
RB051 L-40
(SLF12565TDK) 0.1 uF 10uH
RB051 L-40
BOOT1
VCCCL1
VCCCL2
BOOT2
VCC
0.1 uF
CL1
CL2
OUTH1
1(13) 2(14) 3(15) 4(17) 5(19) 6(21)
OUTH2 SW2 DGND2 OUTL2 VREG5
27(48) 26(47) 25(46) 24(44) 23
Vo(3.3V/3A)
SW1 DGND1 OUTL1
68k
220uF
(OS )
220uF
(OS )
1uF 1uF 13k 15000pF 39k 0.1uF
VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB
10
(25)
47k
1uF
EXTVCC FB2 COMP2 SS2 DET2
18
(36)
22(41) 21(39) 20(38) 19(37)
0.33uF 15k 39k 0.1uF 15000pF
7(22) 8(23) 9(24)
GND
EN1
EN2
11
(26)
12
(27)
13
(29)
14
(31)
15
(33)
16
(34)
100k
Fig-16AStep-DownCout=OS Capacitor There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications.
VIN(12V)
100uF
23m 100 1nF
0.33
23m 10 1nF
32
(7)
SP8K2
RB160 VA-40
uF
100
LLM
17
(35)
RT
SP8K2
RB160 VA-40
36
(12)
35
(11)
34
(10)
33
(8)
31
(5)
30
(3)
29
(2)
28
(1)
(SLF10145TDK) Vo(1.8V/2A) 10uH
RB051 L-40
(SLF10145TDK) 0.1 uF 10uH
RB051 L-40
VCCCL1
VCCCL2
BOOT1
0.1 uF
OUTH1
1(13) 2(14) 3(15)
BOOT2
CL1
VCC
CL2
OUTH2 SW2 DGND2 OUTL2 VREG5
27(48) 26(47) 25(46) 24(44) 23
Vo(2.5V/2A)
SW1 DGND1 OUTL1
3300pF 150
15k 30uF
(C2012JB 0J106K TDK)
30uF 1uF
(C2012JB 0J106K TDK)
43 k
1000pF 510
1uF 1uF 330pF
4(17) 5(19) 6(21)
VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB
10
(25)
EXTVCC FB2 COMP2 SS2 DET2
18
(36)
22(41) 21(39)
12k 10000pF
0.33uF 330pF 20k 3.3k 3300pF 0.1uF
7(22)
1k 0.1uF
8(23) 9(24)
20(38) 19(37)
GND
EN1
EN2
11
(26)
12
(27)
13
(29)
14
(31)
15
(33)
16
(34)
100k
Fig-16BStep-DownCout=Ceramic Capacitor There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications.
6/29
LLM
17
(35)
RT
VIN(12V)
100uF
10m 100 1nF
0.33
10m 10 1nF
32
(7)
Vo(24V/1A)
RB051L-40
L1 (SLF12565TDK) 27uH
REGSPIC
100
TM
uF
SP8K2 RB160 VA-40
27(48) 26(47)
Co1 1000pF 680 k 5.1k
RSS 065N03 220uF 1uF
1(13) 2(14) 3(15) 4(17) 5(19) 6(21) 7(22)
36
(12)
35
(11)
34
(10)
33
(8)
31
(5)
30
(3)
29
(2)
28
(1)
BOOT1
VCCCL1
VCCCL2
BOOT2
VCC
OUTH1 SW1 DGND1 OUTL1
OUTH2 SW2 DGND2 OUTL2 VREG5
0.1 uF
CL1
CL2
(SLF12565TDK) L2 27uH Do3
Vo(12V/1A)
Co2
25(46) 24(44) 23
1uF 1uF 23.5k 22000pF 1000pF 10k 0.1uF
VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB
10
(25)
1uF
RB051 L-40
220 uF
91 k
3300pF 10k
EXTVCC FB2 COMP2 SS2 DET2
18
(36)
22(41) 21(39)
0.33uF 1000pF 6.2k 4.7k 0.1uF 22000pF
8(23) 9(24)
20(38) 19(37)
GND
EN1
EN2
11
(26)
12
(27)
13
(29)
14
(31)
15
(33)
16
(34)
LLM
17
(35)
RT
100k
REGSPICTM is Trade Mark of RHOM
Fig-16CStep-DownLow Input Voltage There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications.
VIN(5V)
100uF
23m 100 1nF
0.33
23m 10 1nF
32
(7)
SP8K2
RB160 VA-40
uF
100
SP8K2
RB160 VA-40
36
(12)
35
(11)
34
(10)
33
(8)
31
(5)
30
(3)
29
(2)
28
(1)
(SLF10145TDK) Vo(1.8V/2A) 6.8uH
RB051 L-40
0.1uF
VCCCL1
VCCCL2
BOOT1
OUTH1
1(13) 2(14) 3(15) 4(17) 5(19) 6(21) 7(22)
BOOT2
CL1
VCC
CL2
0.1uF
OUTH2 SW2 DGND2 OUTL2 VREG5
27(48) 26(47) 25(46) 24(44) 23
(SLF10145TDK) 6.8uH Vo(2.5V/2A)
RB051 L-40
SW1 DGND1 OUTL1
3300pF 100
15k
30uF
()
30uF
()
43 k
1000pF 300
1uF 1uF 12k 4700pF 100pF 3.3k 0.1uF
VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB
10
(25)
1uF
EXTVCC FB2 COMP2 SS2 DET2
18
(36)
22(41) 21(39)
0.33uF 33pF 20k 10k 0.1uF 2200pF
8(23) 9(24)
20(38) 19(37)
GND
EN1
EN2
11
(26)
12
(27)
13
(29)
14
(31)
15
(33)
16
(34)
100k
Fig-16DStep-Upand Step-Up-Down There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications.
7/29
LLM
17
(35)
RT
Application component selection (1) Setting the output L value The coil value significantly influences the output ripple current. Thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lower the drop in ripple current. IL = VCC-VOUTxVOUT LxVCCxf [A] 5
IL
Fig-17
VCC IL L Co
VOUT
The optimal output ripple current setting is 30% of maximum current. IL = 0.3xIOUTmax.[A] 6 L= VCC-VOUTxVOUT ILxVCCxf [H] 7
Fig-18 Output ripple current
ILoutput ripple current
fswitching frequency
Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. Please establish sufficient margin to ensure that peak current does not exceed the coil current rating. Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency. (2) Setting the output capacitor Co value Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage (at rapid load change). The following equation is used to determine the output ripple voltage. IL Step down VPP = IL x RESR + x Co Vcc Vo x f 1 [V] Note: fswitching frequency
Be sure to keep the output Co setting within the allowable ripple voltage range. Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable lower output ripple voltage. Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. Co TSS x (Limit - IOUT) 9 VOUT ILimitover current detection value2/16reference Tss soft start time
Note: less than optimal capacitance values may cause problems at startup. (3) Input capacitor selection VIN Cin VOUT L Co The input capacitor serves to lower the output impedance of the power source connected to the input pin (VCC). Increased power supply output impedance can cause input voltage (VCC) instability, and may negatively impact oscillation and ripple rejection characteristics. Therefore, be certain to establish an input capacitor in close proximity to the VCC and GND pins. Select a low-ESR capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. The ripple current IRMSS is determined using equation (10). IRMS = IOUT x VOUTVCC - VOUT [A] 10 VCC Also, be certain to ascertain the operating temperature, load range and MOSFET conditions for the application in which the capacitor will be used, since capacitor performance is heavily dependent on the application's input power characteristics, substrate wiring and MOSFET gate drain capacity. 8/29
Fig-19 Input capacitor
(4) Feedback resistor design Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range between 10k and 330k. Resistance less than 10k risks decreased power efficiency, while setting the resistance value higher than 330k will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Vo
Internal ref. 0.8V
R8 FB R9 Fig-20
Vo =
R8 +R9 R9
x 0.8 [V] 11
(5) Setting switching frequency The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper RT resistance, noting that the recommended resistance setting is between 50k and 130k. Settings outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when unsupported resistance values are used.
550 500 [ kHz ] 450 400 350 300 250 50 60 70 80 90 RT [ k] 100 110 120 130
Fig-21 RT vs. switching frequency (6) Setting the soft start delay The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right.
10
DELAY TIME[ms]
1
0.8V(typ.)xCSS TSS = ISS(10A Typ.) [sec](12)
0.1
0.01 0.001 0.01 SS CAPACITANCE[uF] 0.1
Fig-22 SS capacitance vs. delay time
Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input voltage, output voltage and capacitance, coils and other characteristics.
9/29
(7) Setting over current detection values The current limit valueILimitis determined by the resistance of the RCL established between CL and VCCCL.
VCCCL CL VIN RCL IL L Vo
IL
Over current detection point
ILimit =
90m RCL
[A](13)
Fig-23
Fig-24
There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin. LOFF=L (0Vo
LOFF=L OFF Latch
The current limit value
Vox70% LOFF=H
Fig-25
Io
(8) Method for determining phase compensation Conditions for application stability Feedback stability conditions are as follows: When gain is 1 (0dB) and phase shift is 150 or less (i.e., phase margin is at least 30): a dual-output high-frequency step-down switching regulator is required Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no more than 1/10 the switching frequency. In summary, target characteristics for application stability are: Phase shift of 150 or less (i.e., phase margin of 30 or more) with gain of 1 (0dB) GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency. Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response. The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay (-180) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the application. GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger capacitor will serve to lower GBW if desired. General use integrator (low-pass filter) Integrator open loop characteristics A (a) -20dB/decade GBW(b) -90 Phase margin Fig-27 -180 point (a) fa = 1 2RCA
Feedback
R FB
A
COMP
Gain [dB]
18 0
1.25[Hz] [Hz]
90
C
Phase 0 [deg] -90 -9 0
0 -18 0 -180
0
point (b) fa = GBW
1 2RC
Fig-26
The error amp is provided with phase compensation similar to that depicted in figures and above and thus serves as the system's low-pass filter. In DC/DC converter applications, R is established parallel to the feedback resistance. 10/29
When electrolytic or other high-ESR output capacitors are used: Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several ). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these locations is -180. However, wherever ESR is present, a 90 phase lead is generated, limiting the net phase margin to -90 in the presence of ESR. Since the desired phase margin is in a range less than 150, this is a highly advantageous approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components. LC resonance circuit Vcc ESR connected Vcc
Vo L C L Fig-28 C
Vo RESR Fig-29
fr =
1 2LC
[Hz]
fr =
Resonance point phase margin -180
resonance point1 [Hz]Resonance Point 2LC 1 fESR = [Hz] :Zero 2RESRC -90:Pole
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose one of the following methods to add the phase lead. Add C to feedback resistor
Vo C1 R1 FB R2 A COMP R2 C2 R1 FB A COMP
Vo
Add R3 to aggregator
R3 C2
Fig-30 Phase lead fz = 1 2C1R1 [Hz] Phase lead fz =
Fig-31 1 2C2R3 [Hz]
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance. When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor: Where low-ESR (on the order of tens of m) output capacitors are employed, a two phase-lead insertion scheme is required, but this is different from the approach described in figure ~, since in this case the LC resonance gives rise to a 180 phase margin/delay. Here, a phase compensation method such as that shown in figure below can be implemented. Phase compensation provided by secondary (dual) phase lead
Vo R1 C1 R3 FB A R2 COMP C2
Phase lead fz1 = Phase lead fz2 =
1 2R1C1 1 2R3C2
[Hz] [Hz] [Hz]
LC resonance frequency fr = Fig-32
1 2LC
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency. This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications.
11/29
9MOSFET selection VCC VDS VGSM1 FET uses Nch MOS VDSVcc VGSM1BOOT-SW interval voltage VGSM2VREG5 Allowable currentvoltage current + ripple current Should be at least the over current protection value Select a low ON-resistance MOSFET for highest efficiency
IL
Vo
VGSM2
VDS
Fig-33 10Schottky barrier diode selection VCC Reverse voltage VRVcc Allowable currentvoltage current + ripple current Should be at least the over current protection value Select a low forward voltage, fast recovery diode for highest efficiency The shoot-through may happen when the input parasitic capacitance of FET is extremely big or the Duty ratio is less than or equal to 10%. Less than or equal to 1000pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this character is affected by PCB layout and components.
Vo
VR
Fig-34
11Sequence function Circuit diagram Timing chart
With EN1, 2 at "H" level, when EN1 goes "L", Vo1 turns OFF, but Vo2 output continues. When EN1 stays "H" and EN2 returns to "H", DET1 is in open state; thus SS2 is asserted, and Vo2 output starts. If Vo2 is 76% of the voltage setting or higher, DET2 goes open and SS1 is asserted, starting Vo1 output.
VCC VREG5
VREG5 EN1 EN2
Vo1
OUTH1 BOOT1 VCC BOOT2 OUTH2
Vo2
SW1 OUTL1 DGND1 FB1 COMP1 SS1 DET2
STB EN1
SW2 OUTL2 DGND2 FB2 COMP2 SS2 DET1
EN2 GND
DET2 SS1 FB1 Vo1
over 76% 0.61V
DET1 SS2 FB2 Vo2
0.56V 0.61V 0.56V
under 70%
over 76%
over 70%
With EN1,2 at "H" level, if Vo1 starts at 76% or more of voltage setting, DET goes open and SS1 is asserted, starting Vo2 output.
A
A With EN2 set "L", if Vo2 goes below 70% the voltage setting, DET2 shorts and SS1 is asserted, turning Vo1 OFF
Same as "A" at left
Fig-35
Fig-36
12/29
Input/Output equivalent circuits
(Items in parentheses apply to VQFP48C)
1(13)27(48)PINSW1SW2 2(14)26(47)PINDGND1DGND2 29(2)35(11)PINBOOT2BOOT1 3(15)25(46)PINOUTL1OUTL2 14(31)PINLOFF 28(1)36(15)PINOUTH1OUTH2 24(44) VREG5 / 4(17)VREG5A
BOOT VREG5
OUTH
OUTL
LOFF 172.2k 100k
SW 300k
DGND 135.8k
16(34)PINSYNC
VREG5
6(21)21(39)PINFB1FB2
VREG5 / VREG5A
8(23)19(37)PINSS1SS2
VREG5 / VREG5A
SYNC 250k
5k
FB
1P
1k 2.5k
SS
2k 50k 100k
10(25)11(26)12(27)PIN STBEN1EN2
VCC
9(24)18(36)PINDET1DET2
VREG5 / VREG5A
15(33)PINRT
VREG5
STB EN
172.2k 135.8k
100k
DET
10k
RT
17(35)PINLLM
30(3)34(10)PINCL2CL1 7(22)20(38)PINCOMP1COMP2 31(5)33(8)PINVCCCL2VCCCL1
VCC VREG5 / VREG5A 5k 5P CL 1k COMP
VREG5A VCCCL LLM 308k VCC
20
5k 5k
22(41)PINEXTVCC 24(44)PINVREG5
VCC EXTVCC
5(19)PINVREG33
VCC VREG5A
4(17)DINVREG5A
VCC
VCC 150k
150k
VREG5
746.32k 255k
VREG33 746.32k 469.06k
VREG5A
13/29
Operation notes 1Absolute maximum ratings Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc. Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider taking physical safety measures to protect the circuits, such as adding fuses. 2GND electric potential Keep the GND terminal potential at the lowest (minimum) potential under any operating condition. 3Thermal design Be sure that the thermal design allows sufficient margin for power dissipation (Pd) under actual operating conditions. 4Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts between the power supply and GND. 5Operation in strong electromagnetic fields Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction. 6Testing on application boards Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure to discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to or removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in the assembly process, and take similar antistatic precautions when transporting or storing the IC. 7) The output FET The shoot-through may happen when the input parasitic capacitance of FET is extremely big or the Duty ratio is less than or equal to 10%. Less than or equal to 1000pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this character is affected by PCB layout and components. 8This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. Relations between each potential may form as shown in the example below, where a resistor and transistor are connected to a pin: With the resistor, when GND Pin A, and with the transistor (NPN), when GNDPin B: The P-N junction operates as a parasitic diode With the transistor (NPN), when GND Pin B: The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the parasitic diode described above.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between circuits, and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P substrate) GND.
Resistor (PINA) (PINB) TransistorNPN C B E (PINB)
P P
P N P
+
N
P
+
P N
+
N P substrate GND
P
+
B N
C E GND
(PINA)
Parasitic element GND
Parasitic element Parasitic element or transistor
Parasitic element or transistor
Fig-37
Fig-38
Fig-39
Fig-40
9GND wiring pattern When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND.
14/29
10In some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the GND. In order to avoid these problems, limiting output pin capacitance to 100F or less and inserting a Vcc series countercurrent prevention diode or bypass diode between the various pins and the Vcc is recommended.
Bypass diode
Countercurrent prevention diode
Vcc
Pin
Fig-41
11Thermal shutdown (TSD) This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run beyond allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and turning all output pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal operation. Note that the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no circumstances should the TSD be used in set design or for any purpose other than protecting the IC against overheating 12The SW pin When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value. Connecting a resistor of several will reduce the electric potential. (See Fig. 43)
Vcc BOOT OUTH SW R Vo OUTL DGND
Fig-42
13Dropout operation When input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the ON interval on the OUTL side MOS is lost, making boost applications and wrap operation impossible. If a small differential between input and output voltage is envisioned for a prospective application, connect the load such that the SW voltage drops to the GND level. Managing this load requires discharging the SW line capacitance (SW pin capacitance: approx. 500pF; OUTL side MOS D-S capacitance; Schottky capacitance). Supported loads can be calculated using the equation below. ILOAD = Output voltage x SW line capacitance 25n
Note that SW line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias circuits are configured as in the example below (Fig. 44). However, the degree to which line capacitance is reduced or operational stability is attained will vary depending on the board layout and components. Therefore, be certain to confirm the effectiveness of these design factors in actual operation before entering mass production. Vcc VREG OUT SW OUT Vo Vcc
Fig-43 15/29
Power dissipation vs. temperature characteristics
PD(W)
HQFN36V 1.0
PD(W)
VQFP48C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150
0.75W 1.1W
POWER DISSIPATIONPd [W]
0.8 0.6 0.4 0.2 0.0 0 25
0.875W
0.56W
50
75
100 125 150
POWER DISSIPATIONPd [W]
AMBIENT TEMPERATORETa []
AMBIENT TEMPERATORETa []
Stand-alone IC Mounted on Rohm standard board 70mm x 70mm x 1.6mm glass-epoxy board
Stand-alone IC Mounted on Rohm standard board 70mmx70mmx1.6mm glass-epoxy board
Part order number
B
D
9
0
1
1
K
V
E
2
ROHM part code
Type/No.
Package type KV VQFP48C EKN HQFN36V
Tape and Reel Information E2 : Embossed carrier tape
HQFN36V
Tape Quantity Direction of feed Embossed carrier tape(with dry pack) 2500pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
1234
1234
Unit:mm
Reel
1pin
When you order , please order in times the amount of package quantity.
1234
1234
Direction of feed
1234
1234
VQFP48C
< Packing information >
Tape Quantity Direction of feed Embossed carrier tape 1500pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
Reel Unit:mm) 16/29
1Pin
Direction of feed
When you order , please order in times the amount of package quantity.
BD9775FV (1channel synchronous rectification configuration) Description BD9775FV is Switching Controller with synchronous rectification(BD9775FV is 1channel synchronous rectification) and wide input range. It can contribute to ecological design(lower power consumption) for most of electronic equipments.
Features (BD9775FV) 1) 2channel Step-Down DC/DC FET driver 2) Synchronous rectification for channel 2 3) Able to synchronize to an external clock signal 4) Over Current Protection (OCP) by monitoring VDS of P channel FET 5) Short Circuit Protection (SCP) by delay time and latch method 6) Under Voltage Lock Out (UVLO) 7) Thermal Shut Down (TSD) 8) Package : SSOP-B28
Applications (BD9775FV) Car navigation system, Car Audio, Display, Flat TV
Absolute maximum ratings (Ta=25)(BD9775FV) Parameter Supply Voltage (VCC to GND) VREF to GND Voltage VREGA to GND Voltage VREGB to VCC Voltage OUT1, OUT2H to VCC Voltage OUT2L to GND Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Junction Temperature Symbol Vcc Vref Vrega Vregb Vouth Voutl Pd Topr Tstg Tjmax Limits 36 7 7 7 7 7 640(*1) -40 to +85 -55 to +125 +125 Units V V V V V V mW
(*1) Without heat sink, reduce to 6.4mW when Ta=25 or above Pd is 850mW mounted on 70x70x1.6mm, and reduce to 8.5mW/ above 25.
17/29
Recommended operating conditionsTa=-25 to +75(BD9775FV) Limits MIN Supply Voltage Oscillating Frequency Timing Resistance Timing Capacitance VCC osc RT CT 6.0 30 10 100 TYP 100 27 470 MAX 30.0 300 56 4700 V KHz K pF
Parameter
Symbol
Units
Electrical characteristics Ta=25VCC=13.2V, fosc=100kHz, CTL1=3V, CTL2=3V(BD9775FV) Limits Min. Whole Device Stand-by Current Circuit Current Reference Voltage VREF Output Voltage Line Regulation Load Regulation Short Output Current Internal Voltage Regulator VREGA Output Voltage VREGB Output Voltage VREGB Dropout Voltage Oscillator Oscillating Frequency Frequency Tolerance Synchronized Frequency FIN Threshold Voltage FIN Input Current Error Amplifier Threshold Voltage INV Input Bias Current Voltage Gain Band Width Maximum Output Voltage Minimum Output Voltage Output Sink Current Output Source Current Vthea Ibias Av Bw Vfbh Vfbl Isink Isource1 Isource2 0.98 -1 2.2 0.5 -170 -200 1.00 70 2.0 2.4 2 -110 -130 18/29 1.02 1 2.6 0.1 5.2 -70 -85 V A dB MHz V V mA A A DC Av=0dB INV=0.5V INV=1.5V FB1,2 Terminal FB1 Terminal FB2 Terminal fosc Dfosc osc2 Vthfin IFIN 90 1.2 -1 100 120 1.4 110 2 1.6 1 kHz % kHz V A VFIN=1.4V RT=27k,CT=470pF Vcc=7 to 18V FIN=120kHz Vrega Vregb Vdregb 4.5 VCC-5.5 5.0 VCC-5.0 1.8 5.5 VCC-4.5 2.2 V V V Switching with COUT=5000pF Switching with COUT=5000pF VREGB to GND Voltage Vref DVli DVlo Ios 2.97 -60 3.00 -22 3.03 10 10 -5 V mV mV mA Io=-1mA Vcc=7 to 18V,Io=-1mA Io=-0.1mA to -2mA Iccst Icc 2.5 4.2 5 7 A mA CTL1,CTL2=0V FB1,FB2=0V Typ. Max.
Parameter
Symbol
Unit
Condition
Synchronized Frequency
Parameter PWM Comparator Threshold Voltage at 0% Threshold Voltage at 100% DTC Input Bias Current FET Driver Sink Current Source Current ON Resistance Rise Time Fall Time Driver's Duty Cycle of Synchronous Rectification SYNC Terminal Voltage
Symbol Min. Vth0 Vth100 Idtc Isink Isource RonN RonP Tr Tf 0.88 1.88 -1 20 -510 7.0 0.7
Limits Typ. 0.98 1.98 36 -320 11.0 1.4 20 100 Max. 1.08 2.08 1 58 -180 17.8 2.2
Unit
Condition
V V A mA mA nsec nsec
FB Voltage FB Voltage
VDS=0.4V VDS=0.4V OUT1,2H,2L : L OUT1,2H,2L : H Switching with COUT=5000pF Switching with COUT=5000pF RSYNC=30K, 50% of main driver's duty cycle Rsync=30K,FB=1.5V
Duty
42
45
48
%
Vsync
1.45
1.55
1.65
V
Over Current Protection (OCP) VS Threshold Voltage Vths IVSH IVSL Icl
VCC-0.24 VCC-0.21 VCC-0.18
V A A A
RCL=21k, the output tern off after detected 8 cycle VS1,VS2=PBU VS1,VS2=0V
VS Input Current CL Input Current Stand-by Threshold Voltage CL Input Current Timer Start Voltage Threshold Voltage Stand-by Voltage Source current
-1 -1 9
10
1 1 11
Vctl Ictl Vtime Vthscp Vstscp Isoscp
1.0 6 0.6 1.92 -4.0
1.5 15 0.7 2.00 10 -2.5
2.0 30 0.8 2.08 100 -1.5
V A V V mV A CTL1,CTL2=3V INV Voltage SCP Voltage SCP Voltage SCP=1.0V
Short Circuit Protection SCP
Under Voltage Lock Out UVLO Threshold Voltage Hysteresis Voltage Range Vuvlo DVuvlo 5.6 0.05 5.7 0.1 5.8 0.15 V V Vcc sweep down
19/29
Pin Description
1
PinNo/PinName (BD9775FV)
FB1 INV1 RT CT Fin GND VREF DTC1 DTC2 INV2 FB2 CTL1 CTL2 VCC VS1 28 CL1 27 PVCC1 26 OUT1 25 VREGB 24 OUT2H 23 PVCC2 22 CL2 VS2 SCP
21 20 19 2 3 4 5 6 7 8 9 10 11 12 13 14
(BD9775FV)
Pin No. 1 2 3 4 5 6 7 8 9 10 11
Pin Name FB1 INV1 RT CT FIN GND VREF DTC1 DTC2 INV2 FB2 CTL1 CTL2 VCC SYNC PGND OUT2L VREGA SCP VS2 CL2 PVCC2 OUT2H VREGB OUT1 PVCC1 CL1 VS1
Description Error amplifier output pinChannel 1 Error amplifier negative input pinChannel 1 Oscillator frequency adjustment pin connected resistor Oscillator frequency adjustment pin connected capacitor Oscillator synchronization pulse signal input pin Low-noise ground Reference voltage output pin Maximum duty and soft start adjustment pinChannel 1 Maximum duty and soft start adjustment pinChannel 2 Error amplifier negative input pinChannel 2 Error amplifier output pinChannel 2 Enable/stand-by control inputChannel 1 Enable/stand-by control inputChannel 2 Main power supply pin Synchronous rectification timing adjustable pin Power ground (connected low-side gate driver and digital ground) Low-side ( synchronous rectifier ) gate driver output pinChannel 2 Connected capacitor for internal regulator Delay time of short circuit protection adjustment pin connected capacitor Over current detection voltage monitor pin connected FET drain, Channel 2 Over current detection voltage adjustment pin connected capacitor and resistorChannel 2 High-side gate driver power supply inputChannel 2 High-side gate driver output pinChannel 2 Connected capacitor for internal regulator High-side gate driver output pinChannel 1 High-side gate driver power supply inputChannel 1 Over current detection voltage adjustment pin connected capacitor and resistorChannel 1 Over current detection voltage monitor pin connected FET drain, Channel 1
VREGA 18 OUT2L 17 PGND 16 SYNC 15
Block Diagram (BD9775FV)
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Fig.1
28
FUNCTION EXPLANATION (BD9775FV) 1.DC/DC Converter Reference Voltage Stable voltage of compensated temperature, is generated from the power supply voltage (VCC). The reference voltage is 3.0V, the accuracy is 1. Place a capacitor with low ESR (several decades m) between VREF and GND. Internal Regulator A VREGA 5V is generated the power supply voltage. The voltage is for the driver of the synchronous rectification's MOSFET. Place a capacitor with low ESR (several decades m) between VREGA and PGND. 20/29
Internal regulator B VREGB (VCC-5V) is generated from the power supply voltage. The voltage is for the driver of the main MOSFET switch. Place a capacitor with low ESR (several decades m) between VREGB and PVCC. Oscillator Placing a resistor and a capacitor to RT and CT, respectively, generates two triangle waves for both cannels, and each wave is opposite phase. The waves are input to the PWM comparators for CH1 and CH2. Also, the oscillating frequency can be slightly adjusted (less than 20%) by putting external clock pulse into Fin pin, which is higher frequency than the fixed one. Error Amplifier It amplifies the difference, between the establish output voltage and the actual output one detected at INV. And amplified voltage comes out from FB. The comparing voltage is 1.0V and the accuracy is 2%. The phase can be compensated externally by placing a resistor and a capacitor between INV and FB. PWM Comparator It converts the output voltage from error amplifier into PWM waveform, then output to MOSFET driver. MOSFET Driver The main drivers (OUT1, OUT2H) are for P-channel MOSFETs, and the driver (OUT2L) for synchronous rectification is for N-channel MOSFET. The values of output voltage are clamp to VREGB, VREGA, respectively. All drivers' output configurations are push-pull type. In addition, the output current capability is 36mA for the sink current and 320mA (Vds=0.4V) for the source current. 2.Channel Control Each output can be individually turned on or off with CTL1 and CTL2. When the CTL is "H" (more than 1.5V), it becomes turned on. 3.Protection Over Current ProtectionOCP When detected over current (detecting drop voltage of the main MOSFET's ON resistance), the MOSFET switch becomes turned off, and the energy on DTC pin is discharged. After discharged, the output restarts automatically. The level of the OCP detection threshold can be set by the resistance, which is connected between VCC and CL. Short Circuit ProtectionSCP When either output goes down and the voltage on INV pin gets lower than 0.7V, a capacitor placed on SCP is started to charge. When the SCP pin becomes more than 2.0V, the main MOSFET switches of both outputs are turned off; then, the outputs are latched. While they are latched, the IC can be reset by restarting VCC or CTL, or discharging SCP. Under Voltage Lock OutUVLO Due to avoiding malfunctions when the IC is started up or the power supply voltage is rapidly disconnected, the main MOSFET switches become off and DTC is discharged when the supply voltage is less than 5.7V. Also, when the output is latched because of SCP function, the latch becomes reset. Due to preventing malfunctions in the case the power supply voltage fluctuate at near UVLO threshold, there is 0.1V hysteresis between the detection and reset voltage of UVLO threshold. Thermal Shut DownTSD Due to preventing breakdown of the IC by heating up, the main MOSFET switches become off and DTC pin is discharged by detecting over temperature of the chip. Due to preventing malfunctions in the case temperature fluctuate at near TSD threshold, there is hysteresis between TSD on and off.
21/29
SETTING UP INFOMATION (BD9775FV) 1)Simultaneously OFF Duty of MOSFETs for Synchronous Rectification The simultaneously OFF duty of both main MOSFET switch and synchronous rectification MOSFET is determined by resistance (Rsync) between SYNC and GND. See Fig. 4. In Synchronous Rectification, insert RFB2-GND (RFB2-GND3xRsync) between FB2 and GND, because it is possible to reduce overshoot(sea fig.2). RFB2-GND decide following formula.
40 35 30
T=-40
fosc=100kHz duty=(t1+t2)/tx100 (%)
T= 25 T=105
t t1 t2
Duty (%)
25 20
OUT2H
15 10 5 0 0 20 40 60 80 100
OUT2L
Rsync (k)
Fig.2 Resistance at FB2-GND setup condition Threshold Voltage at100% Vsync 3xRsync(MAX) -Output Source Current at FB2 2.08 0.4908 Rsync(MAX) +80.7x10
-6
< RFB2-GND < 3xRsync(MIN)
< RFB2-GND < 3xRsync(MIN)
Rsync(MAX)...MAX dispersion range at Rsync
Rsync(MIN)...MIN dispersion range at Rsync
SYNC Rsync
FB2
RFB2-GND
Short SYNC to VREF if the synchronous rectification function is not needed.
VREF
SYNC
Without Synchronous RectificationDon't insert RFB2-GND
22/29
2) Oscillator Synchronization by External Pulse Signal At the operation the oscillator is externally synchronized, input the synchronization signal into Fin in addition to connect a resistor and a capacitor at RT and CT, respectively. Input the external clock pulse on Fin, which is higher frequency than the fixed one. However, the frequency variation should be less than 20%. Also, the duty cycle of the pulse should be set from 10% to 90%.
Fin Fixed with RT and CT CT Synchronized
CT Waveform during Synchronized with External Pulse Short Fin to GND if the function of external synchronization is not needed.
Fin
Without Synchronization Signal
3)Setting the Over Current Threshold Level The OCP detection levelIocpis determined by the ON resistance (RON) of the main MOSFET switch and the resistance (Rcl) which is placed between CL and VCC.
Iocp
Rcl RON
x10-5
[A]
typ.
To prevent a malfunction caused by noise, place a capacitorCcl parallel to Rcl. If OCP function is not needed, short VS to VCC, and short CL to GND.
VCC
Rcl CL Ccl
CL
VCC VS To Main MOSFET Drain VS
With OCP CL, VS Pin Connection
Without OCP
23/29
4)Setting the Time for Short Circuit Protection The time (tscp) from output short to latch activation is determined by the capacitor, Cscp, connected SCP pin. tscp7.96x10 xCscp
5
[sec]
typ.
Short SCP to GND if SCP function is not being used.
SCP
Without SCP
5)Single Channel Operation This device can be used as a single output. DTC,FB,CTL,CL VS,PVCC INV
The connection is as follows; Short to GND Short to VCC Short to VREF
DTC FB CTL CL VS PVCC INV VREF VCC
Single Channel Operation
6)Setting the Oscillating Frequency The oscillating frequency can be set by selecting the timing resistor (RRT)and the timing capacitor (CCT).
Ocsillating Frequency vs. Timing Capacitance (CCT)
Ocsillating Frequency vs. Timing Capacitance (RRT) 1000 Oscillating Frequency (kHz)
1000
Oscillating Frequency (kHz)
CCT=100pF CCT=470pF
RRT=5.1k
100
CCT=1000pF
100
RRT=27k
RRT=100k
10 10 100 Timing Resistance (k) 1000
10 100 1000 Timing Capacitance(pF) 10000
Fig.3
Fig.4
24/29
Timing Chart (BD9775FV) Output ON/OFF, Minimum InputUVLO
VCC
6.0V UVLO is activated at 5.7V
UVLO is inactivated at 5.8V
CTL1 DTC1 Vout1 CTL2 DTC2 Vout2
1.0V 1.0V
Stand-by
Soft start
Fig.5
Over Current Protection, Short Circuit Protection, Thermal Shut Down
CTL1,2 SCP DTC1,2
0.7xfixed output voltage 1.0V Activate TSD Inactivate TSD Activate SCP 2.0V Reset the latch by restarting CTL
Vout1,2
Half short of output OCP detection level
Iout1,2
Inactivate half-short
OCP is activated by detecting 8 consecutive cycles
Fig.6
I/O EQUIVALENT CIRCUIT (BD9775FV)
FB1(1)
VREF VREF VREGA VREGA VCC VCC
FB2(11)
VREF VREF
RT(3)
VCC VCC VREF VREF VCC VCC
VREGA VREGA
FB1 FB1 RT RT
INV1(2),INV2(10)
VREF VREF
VCC VCC
CT(4)
VREF
VREF VCC VCC VREF VREG
FIN(5)
VCC VCC
INV12 INV1,2 FIN FIN
Fig.7 Fig.8 25/29
DTC1(8),DTC2(9)
VREGA VREGA
CTL1(12),CTL2(13)
VCC VCC
VREGA VREGA VCC VCC
SYNC(15)
VREF VREF VCC VCC
VREF VREF
DTC1,2 DTC1,2
CTL1,2 CTL12
SYNC
SYNC
SCP(19)
VCC VREF VREF
OUT2L(17),VREGA(18)
VCC
VREF(7)
VCC VC VREGA VREGA
VCC VCC

OUT2L OUT2L SCP SCP
VREF VREF
PVCC1(26),PVCC2(22) OUT1(25),OUT2H(23),VREGB(24)
VCC VCC
PVCC12 PVCC1,2
VS1(28),VS2(20),CL1(27),CL2(21)
VCC VCC
OUTH12H OUT1,2H CL12 CL1,2 VREGB VREGB VS12 VS1,2
Fig.8
Operation Notes (BD9775FV)
1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. 3) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 5) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. 7) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 8) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance).
26/29
9) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. It is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. Countercurrent prevention diode Vcc Pin
Bypass diode
Fig.9 10) Timing resistor and capacitor Timing resistor(capacitor) connected between RT(CT) and GND, has to be placed near RT(CT) terminal 3pin(4pin). And pattern has to be short enough.
VREF VCC
11) The Dead time input voltage has to be set more than 1.1V. Also, the resistance between DTC and VREF is used more than 30k to work OCP function reliably. 12) The energy on DTC18pinand DTC29pinis discharged when CTL112pinand CTL213pinare OFF, respectively, or VCC14pin is OFF (UVLO activation). However, it is considerable to occur overshoot when CTL and VCC are turned on with remaining more than 1V on the DTC. 13) If Gate capacitance of P-channel MOSFET or resistance placed on Gate is large, and the time from beginning of Gate switching to the end of Drain's (tsw), is long, it may not start up due to the OCP malfunction. To avoid it, select MOSFET or adjust resistance as tsw becomes less than 270nsec.
GATE DRAIN
tsw
Fig.10 14) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins. Resistor (PINA) (PINB) TransistorNPN C B E (PINB)
P P
P N P
+
N
P
+
P N
+
N P substrate GND
P
+
B N
C E GND
(PINA)
Parasitic element GND
Parasitic element Parasitic element or transistor
Parasitic element or transistor
Fig.11
pd(W) 1.0
0.8
0.85W
POWER DISSIPATION pd(W
0.6
0.4
0.64W
0.587W
0.2
With no heat sink Copper laminate area 70 mmx70mm 0 25 50 75 100 125
150
0
AMBIENT TEMPERATURE
Ta()
Fig.12 27/29
Part order number
B
D
9
7
7
5
F
V
-
E
2
ROHM Part Code
Type/No.
Package type FV : SSOP-B28
Tape and Reel Information E2 : Embossed carrier tape
SSOP-B28
Tape Quantity Direction of feed Embossed carrier tape 2000pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
1234
(Unit:mm)
Reel
123
When you order , please order in times the amount of package quantity.
123
1pin
1234
123
Direction of feed
1234
1234
1234
28/29
Catalog No.08T672A '08.9 ROHM (c)
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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